Field of the Invention
The invention relates to an integrated memory having an adjustable latency and a method for setting the latency in the integrated memory. The invention can be used particularly in dynamic random access memories (DRAMs) and synchronous DRAMs (SDRAMs).
An integrated memory generally has a memory cell array that contains word lines and bit lines. In this case, the memory cells are disposed at the crossover points between the bit lines and word lines and are connected via a respective selection transistor, whose control input is connected to one of the word lines, to the bit line, via which a data signal is read or written. For memory access, a control circuit for controlling the memory access generally receives an access instruction in the form of a read instruction or a write instruction. To read or write a data signal, the respective selection transistor for the appropriate memory cell is turned on by an activated word line, as a result of which a data signal of a selected memory cell can subsequently be read or written.
In synchronous, that is to say clock-controlled, data communication, there is a certain time period, the “data latency”, between the instruction that initiates the data transmission and the actual data transmission. If the memory chip in a computer system containing a processor and a memory chip receives a read instruction together with the desired address from the processor, then the memory chip subsequently sends the requested data to the processor. In this case, the data are not sent to the processor immediately, but rather a previously set fixed number of clock cycles later, the “CAS latency” (CL), also referred to as a read latency (RL). The same applies to the write operation. In this case, the processor sends the data to the memory chip delayed by a write latency (WL) after the write instruction.
Both the RL for the read instruction and the WL for the write instruction are permanently set in the mode register of the memory chip, usually when the system starts.
The magnitude of the RL and WL is dependent on the absolute time that the memory chip requires in order to provide the data and on the period duration of the system clock. The latency is defined as the ratio of the time period for providing the data to a clock period. That is to say that the latency, measured in clock cycles, becomes greater the higher the clock frequency becomes. If, for example, the memory chip requires 30 ns for a read operation and a system clock of 100 MHz is applied, which corresponds to a clock period of 10 ns, then a latency of 3 clock cycles is obtained. If, by contrast, a system clock 10 MHz is applied, which corresponds to a clock period of 100 ns, then a latency of 0.3 clock cycles is obtained.
In a large number of mobile applications, for example in the case of personal digital assistants (PDAs), the clock frequency is varied in order to save energy, because the energy consumed rises with the square of the clock frequency. In this case, however, the latency that is set always matches only a particular clock frequency. Normally, the latency is set to the highest occurring clock frequency in this context. If the clock frequency is lowered, the latency is unnecessarily long, which has a negative effect on the data throughput in the system. To change the latency, it is necessary to rewrite information to the mode register, but this takes a relatively large number of clock cycles.
An integrated memory is known in which the CAS latency is received together with the access instruction, that is to say the write or read instruction. To this end, the integrated memory contains a control circuit that is used to receive the CAS latency together with the access instruction. This solution has the drawback that transmitting the CAS latency requires additional signal inputs and hence additional pins on the memory.